Design and chip implementation of a heterogeneous multi-core DSP

  • Authors:

  • Shuming Chen;Xiaowen Chen;Yi Xu;Jianghua Wan;Jianzhuang Lu;Xiangyuan Liu;Shenggang Chen

  • Affiliations:

  • National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China;National University of Defense Technology, Changsha, China

  • Venue:
  • Proceedings of the 16th Asia and South Pacific Design Automation Conference
  • Year:
  • 2011

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Abstract

This paper presents a novel heterogeneous multi-core Digital Signal Processor, named YHFT-QDSP, hosting one RISC CPU core and four VLIW DSP cores. The CPU core is responsible for task scheduling and management, while the DSP cores take charge of speeding up data processing. The YHFT-QDSP provides three kinds of interconnection communication. One is for inner-chip communication between the CPU core and the four DSP cores, the other two for both inner-chip and inter-chip communication amongst DSP cores. The YHFT-QDSP is implemented under SMIC® 130nm LVT CMOS technology and can run 350MHz@1.2V with 114.49 mm2 die area.