Route flap damping exacerbates internet routing convergence
Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
HLP: a next generation inter-domain routing protocol
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Design of a novel statistics counter architecture with optimal space and time efficiency
SIGMETRICS '06/Performance '06 Proceedings of the joint international conference on Measurement and modeling of computer systems
Can you hear me now?!: it must be BGP
ACM SIGCOMM Computer Communication Review
TCP offload is a dumb idea whose time has come
HOTOS'03 Proceedings of the 9th conference on Hot Topics in Operating Systems - Volume 9
Design and implementation of a routing control platform
NSDI'05 Proceedings of the 2nd conference on Symposium on Networked Systems Design & Implementation - Volume 2
Network-wide prediction of BGP routes
IEEE/ACM Transactions on Networking (TON)
Differentiated BGP Update Processing for Improved Routing Convergence
ICNP '06 Proceedings of the Proceedings of the 2006 IEEE International Conference on Network Protocols
Accountable internet protocol (aip)
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
Building a fast, virtualized data plane with programmable hardware
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
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Higher-level Internet protocols are typically designed to be implemented in software. As scaling challenges increase, however, conventional software-based protocol processor architectures start to hit performance walls. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement some of these protocols directly in hardware. Such implementations allow designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance, however, these potential performance gains are reliant on being able to efficiently and effectively process the protocol in hardware. In this paper, we suggest that hardware-based implementations should be considered while designing such protocols. To demonstrate the benefits in this, we study Internet routing, using BGP as a case study. We propose an architecture and logical design for processing BGP in hardware and enumerate sources of complexity and performance bottlenecks. We then compare this to our modified version of BGP which retains the features of BGP but is designed with a hardware implementation in mind. We show that a few changes to the protocol improve processing time and throughput by an order of magnitude.