Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

  • Authors:
  • R. Mahesh;A. P. Vinod;Edmund M-K. Lai;Amos Omondi

  • Affiliations:
  • School of Computer Engineering, Nanyang Technological University, Singapore, Singapore 639798;School of Computer Engineering, Nanyang Technological University, Singapore, Singapore 639798;School of Engineering and Advanced Technology, Massey University, Massey, New Zealand;School of Computing, University of Teeside, Middlesbrough, United Kingdom

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2011

Quantified Score

Hi-index 0.00

Visualization

Abstract

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.