A fully pipelined architecture for the LOCO-I compression algorithm

Authors:
Pierantonio Merlino;Antonio Abramo
Affiliations:
Department of Electrical, Management and Mechanical Engineering, University of Udine, via delle Scienze, Italy;Department of Electrical, Management and Mechanical Engineering, University of Udine, via delle Scienze, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 2
Cited 0

A Parallel Pipelined Implementation of LOCO-I for JPEG-LS

ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 1 - Volume 01
The LOCO-I lossless image compression algorithm: principles and standardization into JPEG-LS

IEEE Transactions on Image Processing

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Abstract

This paper presents the design of a novel architectural implementation of the LOCO-I compression scheme, the lossless/near-lossless algorithm used inside the JPEG-LS standard. Differently from what previously reported in literature, the proposed design fully exploits the sequential nature of the algorithm by means of a pipelined architecture, without modifications to the original compression scheme. The result is a good performance circuit well fitted for field-programmable gate-array realization, thus devised for application in the wearable computers and remote sensing domains.