Random early detection gateways for congestion avoidance
IEEE/ACM Transactions on Networking (TON)
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Providing packet-loss guarantees in DiffServ architectures
PCC '02 Proceedings of the Performance, Computing, and Communications Conference, 2002. on 21st IEEE International
An on-demand queue management architecture for a programmable traffic manager
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A key issue in the design of next-generation Internet routers and switches will be provision of Traffic Manager (TM) functionality in the datapaths of their high-speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping, and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g., drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.