FPGA Based Implementation and Comparison of Beamformers for CDMA2000

  • Authors:

  • Sener Dikmese;Adnan Kavak;Kerem Kucuk;Suhap Sahin;Ali Tangel

  • Affiliations:

  • Department of Communication Engineering, Tampere University of Technology, Tampere, Finland 33720 and Wireless Communications and Information Systems Research Centre, Department of Computer Engine ...;Wireless Communications and Information Systems Research Centre, Department of Computer Engineering, Kocaeli University, Izmit, Kocaeli, Turkey 41380;Department of Electronics and Computer Education, Kocaeli University, Izmit, Kocaeli, Turkey 41380;Wireless Communications and Information Systems Research Centre, Department of Computer Engineering, Kocaeli University, Izmit, Kocaeli, Turkey 41380;Department of Electronics and Communication Engineering, Kocaeli University, Izmit, Kocaeli, Turkey 41380

  • Venue:
  • Wireless Personal Communications: An International Journal
  • Year:
  • 2011

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Abstract

For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming accuracy, FPGA resource utilization, weight vector computation time, and DOA estimation error are presented. Beamformer weight vectors using LMS and CM can be computed within less than 20 μs on Virtex II FPGA and 10 μs on Virtex IV FPGA, and using SCC it can be achieved within less than 22 μs on Virtex IV FPGA. These results show that FPGAs provide approximately 500 times faster speed in implementations than our previous work with DSPs.