A 60 GHz receiver front-end in 65 nm CMOS

  • Authors:

  • Sha Tao;Saul Rodriguez;Ana Rusu;Mohammed Ismail

  • Affiliations:

  • RaMSiS Group, School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden;RaMSiS Group, School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden;RaMSiS Group, School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden;RaMSiS Group, School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2011

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Abstract

In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of 驴13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm 脳 0.44 mm.