Regular Article: Equivalence Relations on Finite Dynamical Systems
Advances in Applied Mathematics
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields
IEEE Transactions on Computers
Generic Systolic Arrays: A Methodology for Systolic Design
TAPSOFT '93 Proceedings of the International Joint Conference CAAP/FASE on Theory and Practice of Software Development
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Fixed points in discrete models for regulatory genetic networks
EURASIP Journal on Bioinformatics and Systems Biology
A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
A highly parameterized and efficient FPGA-based skeleton for pairwise biological sequence alignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multivariate polynomial interpolation is a key computation in many areas of science and engineering and, in our case, is crucial for the solution of the reverse engineering of genetic networks modeled by finite fields. Faster implementations of such algorithms are needed to cope with the increasing quantity and complexity of genetic data. We present a new algorithm based on Lagrange interpolation for multivariate polynomials that not only identifies redundant variables in the data and generates polynomials containing only nonredundant variables, but also computes exclusively on a reduced data set. Implementation of this algorithm to FPGA led us to identify a systolic array-based architecture useful for performing three interpolation subtasks: Boolean cover, distinctness, and polynomial addition. We present a generalization of these tasks that simplifies their mapping to the systolic array, and control and storage considerations to guarantee correct results for input sequences longer than the array. The subtasks were modeled and implemented to FPGA using the proposed architecture, then used as building blocks to implement the rest of the algorithm. Speedups up to 172× and 67× were obtained for the subtasks and complete application, respectively, when compared to a software implementation, while achieving moderate resource utilization.