New hardware architecture for bit-counting

Authors:
Ahmed Dalalah;Sami Baba;Abdallah Tubaishat
Affiliations:
Computer Science Dept., Jordan University of Science and Technology;Computer Science Dept., Applied Science Private University;College of Information Systems, Zayed University
Venue:
ACOS'06 Proceedings of the 5th WSEAS international conference on Applied computer science
Year:
2006

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Abstract

Bit-counting implementations are used to count the number of 1s in a given computer word. There are several techniques to implement -counting operation. These techniques are either software algorithms or specialized hardware techniques. The hardware implementations require hardware supported in the processor or associated math co-processor. The performance hardware-supported bit-counting was found to be superior to most software implementations serial shifting). In this paper, a new hardware implementation of bit-counting routine is presented reduces the number of logic gates and the delay in comparison with existing implementations. performance of the proposed hardware bit-counting implementations is further investigated evaluated.