An overview of hierarchical control flow graph models
WSC '95 Proceedings of the 27th conference on Winter simulation
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Improvement of ASIC Design Processes
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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For optimization of digital circuit, designers encounter number of problems regarding signal and time complexity which are required to be reduced or eliminated. During our research of designing image compression preprocessor, division of main task into comparatively smaller number of subtasks is carried out for the simplification of operation especially with respect to time. This paper presents the methodology to visualize efficient image compression preprocessor design on the basis of task partitioning considering coarse grain architecture. For the boosting of theoretical approach, recursive data extraction from image, purpose of z-transform utilization, signal flow graphs and time complexity for task completion is also incorporated in this paper. Moreover, practical solutions acquired by simulating tools are also assimilated in this paper with appropriate substantiation.