Fault Set Partition for Efficient Width Compression
ATS '02 Proceedings of the 11th Asian Test Symposium
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
Proceedings of the 32nd annual international symposium on Computer Architecture
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The objective of the paper is to design a Modulo-10 Partition Counter as a module written in VHDL. This module generates a repeating sequence of fifty-two partitions under the control of the input clock signal. Each partition is expressed by an array of appropriate integer values based on the mathematical Restricted Growth String notation. A phase difference equal to the half period of the clock signal is used internally to achieve the correct pulse timing of the output. The output signal patterns correspond to the blocks of each partition in a phase encoded format for a duration of ten phases. The VHDL description of the MPC10 module is given and the simulation and synthesis results are presented.