Proceedings of the 27th annual international symposium on Computer architecture
Adaptive History-Based Memory Schedulers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A Burst Scheduling Access Reordering Mechanism
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient memory IP design for HDTV coding applications
IEEE Transactions on Circuits and Systems for Video Technology
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Improvement in digital signal processing makes it better for high speed application. DSP applications such as multimedia and image processing are characterized by colossal amount of data accesses. Today cardinal issue of DSP application is to reduce impact of memory accesses on execution time. Memory Scheduling is important for DSP application to use memory bandwidth effectively. The paper recounts all memory scheduler for DSP application till today. The paper also, introduces dynamic memory access scheduling with refresh priority scheduling. H.264/AVC provides higher coding efficiency through added features and functionality, which impose additional computational complexity in encoder and decoder. The features of memory access patterns of H.264 encoder are analyzed. The overhead cycle of page activation has been reduced to improve bus efficiency which, further adheres to cut down latency of operations. Experiment results from running H.264 application and memory scheduler on Xilinx FPGA. Ultimately, paper compares reduction in execution time with all previous memory scheduler.