A formal model for microprocessor caches

Authors:
Hans Vandierendonck;Jean-Marie Jacquet;Bavo Nootaert;Koen De Bosschere
Affiliations:
Dept. of Electronics and Information Systems, Ghent University, Belgium;Institute of Informatics, University of Namur, Belgium;Dept. of Electronics and Information Systems, Ghent University, Belgium;Dept. of Electronics and Information Systems, Ghent University, Belgium
Venue:
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Year:
2006

Citing 5
Cited 0

A comparative analysis of schemes for correlated branch prediction

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A language for describing predictors and its application to automatic synthesis

Proceedings of the 24th annual international symposium on Computer architecture
Bibliography and reading on CPU cache memories and related topics

ACM SIGARCH Computer Architecture News
Piecewise Linear Branch Prediction

Proceedings of the 32nd annual international symposium on Computer Architecture
Analysis of the O-GEometric History Length Branch Predictor

Proceedings of the 32nd annual international symposium on Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Contemporary processors have reached a bewildering level of complexity featuring multiple execution pipelines, out-of-order instruction issuing, speculative execution, various prediction components and cache memories. The performance of these components is sometimes not well understood. To facilitate the analysis of these components, we propose the use of formal models of these components. Hereby, we aim to lay a formal basis for reasoning on processor components and to formally proove their properties. In this paper, we develop an operational semantics of cache memories and show how it describes operational aspects of caches.