Performance evaluation of superscalar processor with multi-bank register file using SPEC2000

Authors:
Kazuya Tanigawa;Tetsuo Hironaka;Moto Maeda;Tetsuya Sueyoshi;Kenichi Aoyama;Tetsushi Koide;Hans Juergen Mattausch
Affiliations:
Department of Computer Engineering, Hiroshima City University, Hiroshima, Japan;Department of Computer Engineering, Hiroshima City University, Hiroshima, Japan;Department of Computer Engineering, Hiroshima City University, Hiroshima, Japan;Research Center for Nanodevices and Systems, Hiroshima University, Higashi-Hiroshima, Japan;Research Center for Nanodevices and Systems, Hiroshima University, Higashi-Hiroshima, Japan;Research Center for Nanodevices and Systems, Hiroshima University, Higashi-Hiroshima, Japan;Research Center for Nanodevices and Systems, Hiroshima University, Higashi-Hiroshima, Japan
Venue:
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Year:
2006

Citing 8
Cited 0

Multiscalar processors

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Complexity-effective superscalar processors

Proceedings of the 24th annual international symposium on Computer architecture
Reducing the complexity of the register file in dynamic superscalar processors

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
The MIPS R10000 Superscalar Microprocessor

IEEE Micro
Reducing register ports for higher speed and lower energy

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Banked multiported register files for high-frequency superscalar microprocessors

Proceedings of the 30th annual international symposium on Computer architecture
A Scalable Register File Architecture for Dynamically Scheduled Processors

PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Superscalar Processor with Multi-Bank Register File

IWIA '05 Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Recently, register files in highly parallel superscalar processors tend to have large chip area and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the approaches for solving these problems, researchers have proposed several methods using a multi-bank register file instead of multi-port register file. And we have proposed a method to achieve higher performance as compared with other methods. In this paper, we evaluate the effectiveness of our method by software simulation using SPECint2000. The results shows that a superscalar processor with our proposal method has only 1% performance degradation in a cycle-based comparison with a conventional multi-port register file under the condition that each register bank in multi-bank register file has two read ports and two write ports. Additionally, our method keeps only 3% performance degradation even if each bank register has only one port.