FPGA based parallel transitive closure algorithm

Authors:
Zheng Ding;Wei Shu;Min-You Wu
Affiliations:
Shanghai Jiao Tong University, Shanghai, China;University of New Mexico, Albuquerque;Shanghai Jiao Tong University, Shanghai, China
Venue:
Proceedings of the 2011 ACM Symposium on Applied Computing
Year:
2011

Citing 2
Cited 0

A Theorem on Boolean Matrices

Journal of the ACM (JACM)
Measuring the Gap Between FPGAs and ASICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose a FPGA-based parallel algorithm to compute the transitive closure of the relation matrix on a fixed-size PE array. Experimental results showed that speedup increases with the problem size. The speedup against a single PE is between 11.3 and 195.9. Compared to a general CPU solution, this algorithm achieves acceleration rate of 3.7 and 376 under the worst and best situations, respectively.