Novel processor architecture for modified advanced routing in NGN

• Authors: Marija Kalendar;Danijela Jakimovska;Aristotel Tentov;Goce Dokoski
• Venue: Proceedings of the 2011 ACM Symposium on Applied Computing
• Year: 2011

As technology advances, network connection links are gaining higher capacities, and consequently, networking hardware experiences difficulties to timely satisfy such link requests for throughput, bandwidth, speed, and delays. In the given situation, it becomes a necessity to research new ways of augmenting routing performances for achieving respectable speeds. Generalpurpose processors can not always cope with these speeds, and ASIC circuits are not flexible enough. Therefore, combining both approaches seems a very appropriate solution. Additionally, having in mind that in the very near future 10/100 Gb/s network links will dominate, one aspect that might emerge is the possibility of changing the overall routing concept. Due to the continuous and significant memory cost decrease, this paper proposes a modification to the widely used routing process, such that a complete list of all Internet organization domain routers is kept at each organization domain router. In order to pursuit the modified routing process we propose a simple and flexible ASIP architecture for network packet processing that supports this modification. The network processor architecture is based on a 64-bit RISC core with Harvard architecture, customized and optimized for IP packet processing. We expect that this architecture will overcome current network processing speeds, and be able to cope with 10/100 Gb/s links of Next Generation Networks.