Reducing jitter in nonuniform sampling drivers

• Authors: F. Papenfuß;D. Timmermann
• Venue: ICS'06 Proceedings of the 10th WSEAS international conference on Systems
• Year: 2006

It is know for quite some time now (cf. [1-3] and [4]) that practical alias-free signal processing systems utilizing a wider alias free band than set by the sampling theorem can be built successfully through the use of deliberate nonuniform sampling. Such systems are especially useful when processing radio signals digitally. However, such sampling systems usually require a high precision clock generator in order to maintain their full spectral dynamic range throughout their operational bandwidth. Clock generators are referred to as high precision if they expose 3 ps RMS cycle-to-cycle jitter or less. Such generators are expensive and not available over all frequency ranges (affordable support typically ranges from 10 to 170 MHz). Therefore, a robust sampling driver (SD) design written in VHDL or another portable hardware description language will usually utilise a delay locked loop (DLL) or phase locked loop (PLL) to obtain higher frequencies for internal logic producing the desired nonuniform sampling eventually presented to an attached ADC. Unfortunately every DLL or PLL will add jitter to the produced sampling instants thus diminishing spectral dynamic range. In this paper we propose a remedy to afore mentioned added jitter. The proposed jitter reducing methodology is robust and will work in a variety of nonuniform sampling driver designs. The obtained results are verified, using a sampling driver implementation featuring a FPGA, by jitter measurements based on an algorithm reported in [5].