Algorithm-based low-power transform coding architectures: the multirate approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Image and video coding-emerging standards and beyond
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a low power architecture for matrix-vector multiplier of a constant matrix by a vector, which is the main part of the Discrete Cosine Transform (DCT), and the inverse Discrete Cosine transform (IDCT). The proposed architecture makes use of the fact that the input data are mostly zeros, hence it is more suitable for performing IDCT. It avoids unnecessary arithmetic operations by quickly terminating the multiplication by zero and significantly reduces the power and delay. For further reduction in power dissipation, the proposed architecture is designed in a way to eliminate the RAM required for the transposition matrix, as it latch the elements of the matrix and continuously dissipate power. The multiplier circuit play a crucial role in the system and heavily contributes to the power dissipation, thus a special attention is paid to its design. The multiplier's architecture and its simulation results are presented.