Systolic realization of Kohonen neural network

Authors:
Jacek Mazurkiewicz
Affiliations:
Institute of Engineering Cybernetics, Wroclaw University of Technology, Wroclaw, Poland
Venue:
ICANN'05 Proceedings of the 15th international conference on Artificial neural networks: formal models and their applications - Volume Part II
Year:
2005

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Abstract

The paper is focused on partial parallel realization of retrieving phase as well as learning phase of Kohonen neural network algorithms. The method proposed is based on pipelined systolic arrays - an example of SIMD architecture. The discussion is realized based on operations which create the following steps of learning and retrieving algorithms. The data which are transferred among the calculation units are the second criterion of the problem.