Theoretical Computer Science
Characterization of the expressive power of silent transitions in timed automata
Fundamenta Informaticae
Performance Evaluation of Polling-Based Communication Systems Using SPNs
Application of Petri Nets to Communication Networks, Advances in Petri Nets
Model-Checking Algorithms for Continuous-Time Markov Chains
IEEE Transactions on Software Engineering
Optimal state-space lumping in Markov chains
Information Processing Letters
Model Checking Markov Chains with Actions and State Labels
IEEE Transactions on Software Engineering
Almost-Sure Model Checking of Infinite Paths in One-Clock Timed Automata
LICS '08 Proceedings of the 2008 23rd Annual IEEE Symposium on Logic in Computer Science
Automatic verification of probabilistic concurrent finite state programs
SFCS '85 Proceedings of the 26th Annual Symposium on Foundations of Computer Science
Quantitative Model-Checking of One-Clock Timed Automata under Probabilistic Semantics
QEST '08 Proceedings of the 2008 Fifth International Conference on Quantitative Evaluation of Systems
Distributed Markovian Bisimulation Reduction aimed at CSL Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Model Checking Timed and Stochastic Properties with CSL^{TA}
IEEE Transactions on Software Engineering
Quantitative Model Checking of Continuous-Time Markov Chains Against Timed Automata Specifications
LICS '09 Proceedings of the 2009 24th Annual IEEE Symposium on Logic In Computer Science
The Ins and Outs of the Probabilistic Model Checker MRMC
QEST '09 Proceedings of the 2009 Sixth International Conference on the Quantitative Evaluation of Systems
Bisimulation minimisation mostly speeds up probabilistic model checking
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Performance evaluation and model checking join forces
Communications of the ACM
Stochastic real-time games with qualitative timed automata objectives
CONCUR'10 Proceedings of the 21st international conference on Concurrency theory
Simple O(m log n) time Markov chain lumping
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Fixed-delay events in generalized semi-Markov processes revisited
CONCUR'11 Proceedings of the 22nd international conference on Concurrency theory
Time-bounded verification of CTMCs against real-time specifications
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Observing continuous-time MDPs by 1-clock timed automata
RP'11 Proceedings of the 5th international conference on Reachability problems
Verification of linear duration properties over continuous-time markov chains
Proceedings of the 15th ACM international conference on Hybrid Systems: Computation and Control
Monitor-Based statistical model checking for weighted metric temporal logic
LPAR'12 Proceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Weighted lumpability on markov chains
PSI'11 Proceedings of the 8th international conference on Perspectives of System Informatics
The quest for minimal quotients for probabilistic automata
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Approximating acceptance probabilities of CTMC-paths on multi-clock deterministic timed automata
Proceedings of the 16th international conference on Hybrid systems: computation and control
Backward Solution of Markov Chains and Markov Regenerative Processes: Formalization and Applications
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of linear duration properties over continuous-time markov chains
ACM Transactions on Computational Logic (TOCL)
On-the-fly verification and optimization of DTA-properties for large Markov chains
Formal Methods in System Design
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This paper makes verifying continuous-time Markov chains (CTMCs) against deterministic timed automata (DTA) objectives practical. We show that verifying 1-clock DTA can be done by analyzing subgraphs of the product of CTMC C and the region graph of DTA A. This improves upon earlier results and allows to only use standard analysis algorithms. Our graph decomposition approach naturally enables bisimulation minimization as well as parallelization. Experiments with various examples confirm that these optimizations lead to significant speed-ups. We also report on experiments with multiple-clock DTA objectives. The objectives and the size of the problem instances that can be checked with our prototypical tool go (far) beyond what could be checked so far.