A new approach to the maximum-flow problem
Journal of the ACM (JACM)
An O(n2 log n) parallel max-flow algorithm
Journal of Algorithms
A parallel algorithm for finding a blocking flow in an acyclic network
Information Processing Letters
On the parallel implementation of Goldberg's maximum flow algorithm
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
A parallel blocking flow algorithm for acyclic networks
Journal of Algorithms
An analysis of the highest-level selection rule in the preflow-push max-flow algorithm
Information Processing Letters
Fpga-based prototype of a pram-on-chip processor
Proceedings of the 5th conference on Computing frontiers
Using simple abstraction to reinvent computing for parallelism
Communications of the ACM
Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture
IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Better speedups using simpler parallel programming for graph connectivity and biconnectivity
Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores
Brief announcement: speedups for parallel graph triconnectivity
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures
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We present a parallel solution to the Maximum-Flow (Max-Flow) problem, suitable for a modern many-core architecture. We show that by starting from a PRAM algorithm, following an established "programmer's workflow" and targeting XMT, a PRAM-inspired many-core architecture, we achieve significantly higher speed-ups than previous approaches. Comparison with the fastest known serial max-flow implementation on a modern CPU demonstrates for the first time potential for orders-of-magnitude performance improvement for Max-Flow. Using XMT, the PRAM Max-Flow algorithm is also much easier to program than for other parallel platforms, contributing a powerful example toward dual validation of both PRAM algorithmics and XMT.