Design of a high-performance clock recovery method using PLL

  • Authors:

  • Vahid Javadian;Hadi NourBakhsh;Mohammad Ali Salavati;Reza Kazemi

  • Affiliations:

  • School of Electrical Engineering, Sharif University of Technology, Tehran, Iran;School of Electrical Engineering, Sharif University of Technology, Tehran, Iran;School of Electrical Engineering, Sharif University of Technology, Tehran, Iran;School of Electrical Engineering, Sharif University of Technology, Tehran, Iran

  • Venue:
  • ACELAE'11 Proceedings of the 10th WSEAS international conference on communications, electrical & computer engineering, and 9th WSEAS international conference on Applied electromagnetics, wireless and optical communications
  • Year:
  • 2011

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Abstract

This paper deals with the problem of clock recovery in communication links. Concerning the fact that in the digital world most of the data is transmitted in serial format, a lot of systems send the signal and the clock simultaneously. In this paper, an innovative method for extracting the clock in such systems is introduced. The method relies on the a PLL-like feedback loop that can lock on the input clock with in outstandingly short time. The method has proven to be quite effective in simulations. The applications vary from computer networks to wireless communication. Moreover, It can be quite useful in instrumentation purposes in which the link is the bottleneck of system stability.