Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling
Proceedings of the Conference on Design, Automation and Test in Europe
Error patterns in MLC NAND flash memory: measurement, characterization, and analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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NAND flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as flash memory manufacturers scale to smaller process technologies and store more bits per cell, the reliability and endurance of flash memory are decreasing. Wear-leveling and error correction coding can significantly improve both reliability and endurance, but finding effective algorithms requires quick and accurate characterization of flash memory error patterns. To this end, we have designed and implemented an FPGA-based open framework for quick, accurate, and comprehensive characterization of flash memories. Using this framework, we characterized detailed error patterns of flash memory throughout its entire lifetime. Our implementation uses an error accelerator block to decrease the test time by 20x. Based on these results, we propose and evaluate a smart bad block management policy in flash translation layer to increase SSD lifetime by up to 51%.