Generalized best-first search strategies and the optimality of A*
Journal of the ACM (JACM)
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Steiner's problem in graphs: heuristic methods
Discrete Applied Mathematics - Special issue: combinatorial methods in VLSI
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Improved Steiner tree approximation in graphs
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On the Implementation of MST-Based Heuristics for the Steiner Problem in Graphs
ALENEX '02 Revised Papers from the 4th International Workshop on Algorithm Engineering and Experiments
An algebraic approach to network coding
IEEE/ACM Transactions on Networking (TON)
FLUTE: fast lookup table based wirelength estimation technique
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Network coding for routability improvement in VLSI
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Efficient Rerouting Algorithms for Congestion Mitigation
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Polynomial time algorithms for multicast network code construction
IEEE Transactions on Information Theory
MR: a new framework for multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the advent of smaller devices, a significant increase in the density of on-chip components has raised congestion and overflow as critical issues in VLSI physical design automation. In this paper, we present novel techniques for reducing congestion and minimizing overflows. Our methods are based on ripping up nets that go through the congested areas and replacing them with congestion-aware topologies. Our contributions can be summarized as follows. First, we present several efficient algorithms for finding congestion-aware Steiner trees that is, trees that avoid congested areas of the chip. Next, we show that the novel technique of network coding can lead to further improvements in routability, reduction of congestion, and overflow avoidance. Finally, we present an algorithm for identifying efficient congestion-aware network coding topologies. We evaluate the performance of the proposed algorithms through extensive simulations.