A VLSI architecture for a real-time code book generator and encoder of a vector quantizer

Authors:
Kevin Tsang;Belle W. Y. Wei
Affiliations:
Department of Electrical Engineering, San Jose, State University, San Jose, CA;Department of Electrical Engineering, San Jose, State University, San Jose, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 3
Cited 0

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Adaptive VLSI data compression

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Vector quantization and signal compression

Vector quantization and signal compression

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Abstract

Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator and encoder of 512 × 512 images at 30 frameds. The four-chip 0.8 µm CMOS design implements a tree of Kohonen Self-Organizing Maps, and consists of two VQ processors and two image buffer memory chips. The pipelined VQ processor contains a computational core for both code book generation and encoding, and is scalable to processing larger frames.