Analog ASIC for improved temperature drift compensation of a high sensitive porous silicon pressure sensor

  • Authors:

  • N. P. Futane;S. Roychowdhury;C. Roychaudhuri;H. Saha

  • Affiliations:

  • Department of Electronics and Communication Engineering, Government Polytechnic College, Mumbai, India;Centre for VLSI and Embedded Systems Technology, IIIT Hyderabad, Gachibowli, Hyderabad, India;Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University, Shibpur, Howrah, India;Centre of Excellence for Green Energy and Sensor Systems, Bengal Engineering and Science University, Shibpur, Howrah, India

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2011

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Abstract

The paper focuses on the design of a CMOS analog ASIC for temperature-drift compensation of a high sensitivity piezoresistive micro-machined porous silicon pressure sensor to avoid analog-to-digital conversion, limit chip area and reduce power consumption. For implementing the compensation circuitry, multilayered perceptron (MLP) based artificial neural network (ANN) with inverse delayed function model of neuron has been optimized. The temperature drift compensation CMOS ASIC has been implemented to make porous silicon pressure sensor an excellent SMART porous silicon pressure sensor. Using the compensation circuit, the error in temperature-drift has been minimized from 93% to about 0.5% as compared to 3% using conventional neuron model in the temperature range of 25---80°C. The entire circuit has been designed using 0.35 μm AMS technology model and simulated using mentor graphics ELDO Simulator.