A CMOS Mixed Signal Simultaneous Bidirectional Signaling I/O
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
Design of D-PHY chip for mobile display interface supporting MIPI standard
Microelectronics Journal
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In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8V, 0.18@mm digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8Gb/s data transfer rate over a FR4 PCB trace of length 7.5in. for a target bit-error rate (BER) of 10^-^1^2. The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100MHz to 20GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are 1.76@mA and 5.34mV, respectively. The standalone power consumption of the hybrid is 14.64mW.