The fast Fourier transform and its applications
The fast Fourier transform and its applications
Co-array Fortran for parallel programming
ACM SIGPLAN Fortran Forum
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
The SPMD Model: Past, Present and Future
Proceedings of the 8th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Image Indexing Using Color Correlograms
CVPR '97 Proceedings of the 1997 Conference on Computer Vision and Pattern Recognition (CVPR '97)
Acceleration of a 2D-FFT on an Adaptable Computing Cluster
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Feature Extraction: Foundations and Applications (Studies in Fuzziness and Soft Computing)
Feature Extraction: Foundations and Applications (Studies in Fuzziness and Soft Computing)
Scaling communication-intensive applications on BlueGene/P using one-sided communication and overlap
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
SCF: A Framework for Task-Level Coordination in Reconfigurable, Heterogeneous Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A remote memory access infrastructure for global address space programming models in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Reconfigurable Computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this article, we extend the traditional Partitioned Global Address Space (PGAS) model to provide a multilevel integration of memory, which simplifies development of parallel applications for such systems and improves developer productivity. The new multilevel-PGAS programming model captures the unique characteristics of reconfigurable HPC systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. Based on this model, we extend and adapt the SHMEM communication library to become what we call SHMEM+, the first known SHMEM library enabling coordination between FPGAs and CPUs in a reconfigurable, heterogeneous HPC system. Applications designed with SHMEM+ yield improved developer productivity compared to current methods of multidevice RC design and exhibit a high degree of portability. In addition, our design of SHMEM+ library itself is portable and provides peak communication bandwidth comparable to vendor-proprietary versions of SHMEM. Application case studies are presented to illustrate the advantages of SHMEM+.