The platforms enabling wireless sensor networks
Communications of the ACM - Wireless sensor networks
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Ultra-low power data storage for sensor networks
Proceedings of the 5th international conference on Information processing in sensor networks
Wireless sensor network survey
Computer Networks: The International Journal of Computer and Telecommunications Networking
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
Journal of Signal Processing Systems
An accelerator-based wireless sensor network processor in 130nm CMOS
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Congestion-aware, loss-resilient bio-monitoring sensor networking for mobile health applications
IEEE Journal on Selected Areas in Communications - Special issue on wireless and pervasive communications for healthcare
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human
On-node processing of ECG signals
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
Understanding dc behavior of subthreshold CMOS logic through closed-form analysis
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Communications Magazine
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In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as they are powered by scavengers. In this article, we present an ultra-low power processing system for a wireless sensor node for very low duty cycle applications. In the CoolBio system-on-chip, we utilized several power reduction techniques at both the architecture level and the circuit level. These techniques include feature extraction, voltage and frequency scaling, clock and power gating and a redesign of key standard cells. In the design of the ultra-low power processing system, we paid special attention to the memory subsystem, as it is one of the most power-consuming modules in a design. We also designed a clock manager in order to reduce the power consumed by clocking, and a power manager that is able to power-off unutilized modules. The proposed wireless sensor node processing system consumes 36.4μW at 100MHz and 1.2V supply voltage, for a heartbeat-detection algorithm with a 0.01% duty cycle.