Design and development of a CPU scheduler simulator for educational purposes using SDL

Authors:
Manuel Rodríguez-Cayetano
Affiliations:
Department of Signal Theory and Telematics Engineering, University of Valladolid, Valladolid, Spain
Venue:
SAM'10 Proceedings of the 6th international conference on System analysis and modeling: about models
Year:
2010

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Abstract

This paper presents the design and development of a CPU scheduler simulator using SDL. This simulator enables us to study the behavior of one level and multilevel queue scheduling algorithms (including the real-time ones), and to obtain performance statistics for algorithm evaluation. In addition, a multi-platform graphical user interface, based on the Tcl/Tk language, has been developed to simplify the simulator use. The paper also presents our experiences in using SDL for the specification of CPU scheduling algorithms for educational purposes.