VLSI analogs of neuronal visual processing: a synthesis of form and function
VLSI analogs of neuronal visual processing: a synthesis of form and function
Test infrastructure for address-event-representation communications
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
A FPGA spike-based robot controlled with neuro-inspired VITE
IWANN'13 Proceedings of the 12th international conference on Artificial Neural Networks: advances in computational intelligence - Volume Part I
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This paper presents a hierarchical neuromorphic system for tracking objects. We use AER (Address Event Representation) for transmitting and processing visual information provided by an asynchronous temporal contrast silicon retina. Two AER processing layers work in cascade for firstly detecting different objects, and secondly tracking them even with crossing trajectories. The output of the system offers not only the position of the tracked object but also the speed in pixels per second. The system is fully hardware implemented on FPGA (Spartan II 200), which is part of the USB-AER platform developed in part by authors. A 97.2% of the Spartan II is used for 128×128 pixels input resolution and 6 maximum objects recognition and tracking.