An error tolerance scheme for 3D CMOS imagers
Proceedings of the 47th Design Automation Conference
Image quality assessment: from error visibility to structural similarity
IEEE Transactions on Image Processing
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A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array is promising for high throughput imaging applications. The design specifications of the ADC array in the imager, which jointly and concurrently converts the pixel data to produce a final image, must consider both intra-ADC linearity and inter-ADC uniformity. In this paper, we investigate the relationship between the image quality and the linearity of individual ADCs as well as the uniformity of neighboring ADCs in the array. With the insights to this relationship, the specification requirements for the ADC array can be derived based on a desired level of image quality.