Invasive MPI on intel's single-chip cloud computer
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Wait-Free message passing protocol for non-coherent shared memory architectures
EuroMPI'12 Proceedings of the 19th European conference on Recent Advances in the Message Passing Interface
APE: accelerator processor extensions to optimize data-compute co-location
Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
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As part of our Tera-scale Computing Research Program, Intel Labs has created a second generation experimental "Single-chip Cloud Computer" (SCC). It contains the most Intel Architecture cores ever integrated on a silicon CPU chip: 48 cores. It incorporates technologies intended to scale multi-core processors to 100 cores and beyond, such as an on-chip network, advanced power management technologies and support for message-passing. Architecturally, SCC is a microcosm of a cloud data-center. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over the on-die packet-based network fabric, thus supporting the "scale-out" message passing programming models that have been proven to scale to 1000s of processors in cloud data-centers. The SCC serves as an experimental platform for a wide range of software research and is currently being used by a worldwide community of academic and industry co-travelers. This talk will describe the architecture of the SCC platform and discuss its role in the broader context of our Tera-scale research. For more information, see www.intel.com/info/scc