Correlation bounds for poly-size AC0 circuits with n1-o(1) symmetric gates

• Authors: Shachar Lovett;Srikanth Srinivasan
• Venue: APPROX'11/RANDOM'11 Proceedings of the 14th international workshop and 15th international conference on Approximation, randomization, and combinatorial optimization: algorithms and techniques
• Year: 2011

Average-case circuit lower bounds are one of the hardest problems tackled by computational complexity, and are essentially only known for bounded-depth circits with AND,OR,NOT gates (i.e. AC0). Faced with this adversity, one line of research has been to gradually augment AC0 circuits with a small number of more general gates. Most results to date give lower bounds for quasi-polynomial size AC0 circuits augmented by a poly-logarithmic number of gates, and the correlation bounds obtained are inverse quasi-polynomial. We continue this line of research, but restrict our attention to polynomial size AC0 circuits. Surprisingly, we show that this restriction allows us to prove much stronger results: we can augment the AC0 circuit with n1-o(1) many gates, and still obtain inverse exponential correlation bounds. Explicitly, 1. Poly-size AC0 circuits with n1-o(1) arbitrary symmetric gates have exponentially small correlation with an explicitly given function. 2. Poly-size AC0 circuits with n1/2-o(1) threshold gates have exponentially small correlation with the same explicit function. 3. Poly-size AC0 circuits with n1-o(1) counting gates modulo s have exponentially small correlation with the sum of the bits modulo q, where s, q are co-prime. Our proof techniques combine the meet-in-the-middle approach for circuit lower bounds with restrictions (due to Ajtai) that are tailored to polynomial-size circuits.