Deriving an efficient FPGA implementation of a low density parity check forward error corrector

  • Authors:
  • Andy Gill;Andrew Farmer

  • Affiliations:
  • University of Kansas, Lawrence, KS, USA;University of Kansas, Lawrence, KS, USA

  • Venue:
  • Proceedings of the 16th ACM SIGPLAN international conference on Functional programming
  • Year:
  • 2011

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Abstract

Creating correct hardware is hard. Though there is much talk of using formal and semi-formal methods to develop designs and implementations, in practice most implementations are written without the support of any formal or semi-formal methodology. Having such a methodology brings many benefits, including improved likelihood of a correct implementation, lowering the cost of design exploration and lowering the cost of certification. In this paper, we introduce a semi formal methodology for connecting executable specifications written in the functional language Haskell to efficient VHDL implementations. The connection is performed by manual edits, using semi-formal equational reasoning facilitated by the worker/wrapper transformation, and directed using commutable functors. We explain our methodology on a full-scale example, an efficient Low-Density Parity Check forward error correcting code, which has been implemented on a Virtex-5 FPGA.