Hierarchical Parallelization of an H.264/AVC Video Encoder
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition
HPCC '07 Proceedings of the 3rd international conference on High Performance Computing and Communications
Adaptive slice-level parallelism for H.264/AVC encoding using pre macroblock mode selection
Journal of Visual Communication and Image Representation
A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor
PCM '09 Proceedings of the 10th Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
A software-based MPEG-4 video encoder using parallel processing
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Design and implementation of parallel video encoding strategies using divisible load analysis
IEEE Transactions on Circuits and Systems for Video Technology
Efficient programming paradigm for video streaming processing on TILE64 platform
The Journal of Supercomputing
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Implementation of video coding systems such as H.264/AVC and AVS on multi-core and many-core platforms is attracting much attention. The slice-level parallelism is popular in parallel video coding for its simplicity and flexibility, however, the video quality loses greatly since the partitioning of slices breaks the dependency between macro-blocks, especially on multi-core or many-core platforms. To address this problem, we propose a Macro-Block Group (MBG) parallel scheme for parallel AVS coding. In the proposed scheme, video frames are equally divided into rectangular MBG regions; each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme. Given that MBG is not syntactically supported by AVS, a vertical partitioning scheme is introduced. Additionally, we use mode confining and motion vector difference adjusting techniques to keep consistent with the standard. Two MBG parallel schemes (5驴脳驴9 MBG partition and 8驴脳驴7 MBG partition) are developed on a TILE64 many-core platform, where P/B frames use the MBG parallel scheme and I frames use the macro-block-level parallelism. Experimental results show that the proposed scheme of 5驴脳驴9 MBG partition can achieve a reduction of 52% (IPPP) and 41% (IBBP) quality loss while keeping the same speed-up compared with the slice-level parallelism. With more cores employed, the scheme of 8驴脳驴7 MBG partition gains 23.9 times of speed-up compared with the single-core implementation and achieves similar coding performance as the 5驴脳驴9 scheme.