Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

  • Authors:
  • Alena Simalatsar;Yusi Ramadian;Kai Lampka;Simon Perathoner;Roberto Passerone;Lothar Thiele

  • Affiliations:
  • EPFL, Lausanne, Switzerland;University of Trento, Trento, Italy;ETHZ, Zurich, Switzerland;ETHZ, Zurich, Switzerland;University of Trento, Trento, Italy;ETHZ, Zurich, Switzerland

  • Venue:
  • CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
  • Year:
  • 2011

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Abstract

This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPA-RTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e.g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness.