Software logical structure verification method by modeling implemented specification

Authors:
Keiji Uetsuki;Tohru Matsuodani;Kazuhiko Tsuda
Affiliations:
Graduate School of Systems and Information Engineering, University of Tsukuba, Japan;Debug Engineering Institute;Graduate School of Systems and Information Engineering, University of Tsukuba, Japan
Venue:
KES'11 Proceedings of the 15th international conference on Knowledge-based and intelligent information and engineering systems - Volume Part III
Year:
2011

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Abstract

In component testing for a single function, a functional black box testing based on specification of the function and a white box testing based on the program structure are performed. However, It is difficult to verify a logical correctness of the program by these testing methods. In this paper, a novel verification method to achieve it is proposed. Conventional testing usually compares output from program with expected output, our method models the function specification and the implemented specification as a Decision Table format, then compare them. We applied this method to some commercial programs. As a result, we could verify correctness of the logics implemented in the programs.