Exponentiation cryptosystems on the IBM PC
IBM Systems Journal
TinyECC: A Configurable Library for Elliptic Curve Cryptography in Wireless Sensor Networks
IPSN '08 Proceedings of the 7th international conference on Information processing in sensor networks
Energy-Efficient Implementation of ECDH Key Exchange for Wireless Sensor Networks
WISTP '09 Proceedings of the 3rd IFIP WG 11.2 International Workshop on Information Security Theory and Practice. Smart Devices, Pervasive Systems, and Ubiquitous Networks
Enabling full-size public-key algorithms on 8-bit sensor nodes
ESAS'07 Proceedings of the 4th European conference on Security and privacy in ad-hoc and sensor networks
NanoECC: testing the limits of elliptic curve cryptography in sensor networks
EWSN'08 Proceedings of the 5th European conference on Wireless sensor networks
Efficient implementation of public key cryptosystems on mote sensors (short paper)
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
Improved multi-precision squaring for low-end RISC microcontrollers
Journal of Systems and Software
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Multi-precision multiplication is one of the most fundamental operations on microprocessors to allow public-key cryptography such as RSA and Elliptic Curve Cryptography (ECC). In this paper, we present a novel multiplication technique that increases the performance of multiplication by sophisticated caching of operands. Our method significantly reduces the number of needed load instructions which is usually one of the most expensive operation on modern processors. We evaluate our new technique on an 8-bit ATmega128 microcontroller and compare the result with existing solutions. Our implementation needs only 2, 395 clock cycles for a 160-bit multiplication which outperforms related work by a factor of 10% to 23 %. The number of required load instructions is reduced from 167 (needed for the best known hybrid multiplication) to only 80. Our implementation scales very well even for larger Integer sizes (required for RSA) and limited register sets. It further fully complies to existing multiply-accumulate instructions that are integrated in most of the available processors.