Proceedings of the 19th international conference on Parallel architectures and compilation techniques
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The evolution of processor architectures from multi-core to many-core requires programmers to use concurrency to achieve performance. Unfortunately, shared memory parallel programs are difficult to implement correctly, and so is detecting concurrency bugs (e.g., data races, deadlocks, order violations, atomicity violations). In practice, the most common concurrency bugs are a) data races that arise due to unguarded or improperly guarded memory updates and b) deadlocks that arise due to circular dependencies among locks. While data races can be ameliorated by appropriate synchronization (a challenging problem in itself), deadlocks require fairly complex deadlock avoidance techniques, which may fail when the order of lock acquisitions is not known a priori. Furthermore, due to the potential for deadlocks, programmers cannot arbitrarily compose lock based codes without knowing the internal locking structure. Hence, composability is limited by deadlocks. The goal of this research is to achieve composability of lock based codes.