Efficient parallel learning algorithms for neural networks
Advances in neural information processing systems 1
Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations
DARPA Neural Network Stdy
| Hi-index | 0.00 |
Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.