FPGA implementation of stereo disparity with high throughput for mobility applications

  • Authors:

  • Carlos Y. Villalpando;Arin Morfopolous;Larry Matthies;Steven Goldberg

  • Affiliations:

  • Jet Propulsion Laboratory, California Institute of Technology, Pasadena, 91109, USA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, 91109, USA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, 91109, USA;Indelible Systems, Inc, 8921 Quartz Ave, Northridge, CA 91311, USA

  • Venue:
  • AERO '11 Proceedings of the 2011 IEEE Aerospace Conference
  • Year:
  • 2011

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Abstract

High speed stereo vision can allow unmanned robotic systems to navigate safely in unstructured terrain, but the computational cost can exceed the capacity of typical embedded CPUs. 1 2 In this paper, we describe an end-to-end stereo computation co-processing system optimized for fast throughput that has been implemented on a single Virtex 4 LX160 FPGA. This system is capable of operating on images from a 1024x768 3CCD (true RGB) camera pair at 15Hz. Data enters the FPGA directly from the cameras via Camera Link and is rectified, pre-filtered and converted into a disparity image all within the FPGA, incurring no CPU load. Once complete, a rectified image and the final disparity image are read out over the PCI bus, for a bandwidth cost of 68MB/sec. Within the FPGA there are 4 distinct algorithms: Camera Link capture, Bilinear rectification, Bilateral subtraction pre-filtering and the Sum of Absolute Difference (SAD) disparity. Each module will be described in brief along with the data flow and control logic for the system. The system has been successfully fielded upon the Carnegie Mellon University's National Robotics Engineering Center (NREC) Crusher system during extensive field trials in 2007 and 2008 and is being implemented for other surface mobility systems at JPL.