Thread scheduling for heterogeneous multicore processors using phase identification
ACM SIGMETRICS Performance Evaluation Review
Energy-efficient scheduling on heterogeneous multi-core architectures
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
An efficient and comprehensive scheduler on Asymmetric Multicore Architecture systems
Journal of Systems Architecture: the EUROMICRO Journal
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Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higher-performance cores to achieve advantageous power/performance tradeoffs. Unfortunately, such processors also create unique challenges in effective mapping of processes to cores. The greater the diversity of cores, the more complex this problem becomes. Previous scheduling approaches sample performance while permuting the schedule across each type of core each time a change in application behavior is detected. However, approaches that require frequent sampling of the performance of threads (or combinations of threads) on each core may be impractical. We propose scheduling threads on a heterogeneous multicore processor using not just the detection of a change in program behavior or phase, but instead an identification and recording of these phase behaviors. We highlight the correlation between the execution phases of an application and the performance of those phases on any particular core type. We present mechanisms that exploit this correlation between program phases and appropriate scheduling decisions and demonstrate near optimal mapping of thread segments to processor cores can be done without frequently sampling the performance of each thread on each processor core type.