Cache protocols with partial block invalidations

Authors:
Chen; Dubois
Affiliations:
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA;Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Venue:
IPPS '93 Proceedings of the 1993 Seventh International Parallel Processing Symposium
Year:
1993

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Abstract

The authors introduce hardware cache protocols in which invalidations affect only part of a cached block so that the processor can keep reading the valid part. On a cache miss the entire block is fetched in the cache. The proposed protocols take advantage of the prefetching effects associated with large block sizes while reducing the false sharing miss rate. It does not rely on synchronization as other previous proposals do and therefore it is applicable to systems under any memory consistency model including sequential consistency. Simulation results show that protocols with partial block invalidations may provide significant miss rate and memory traffic reductions over protocols with invalidations of entire blocks. The hardware cost is low and the protocol complexity is only marginally increased.