Data prefetching strategies for vector cache memories

  • Authors:
  • Fu; Patel

  • Affiliations:
  • Center for Reliable & High-Performance Comput., Illinois Univ., Urbana-Champaign, IL, USA;Center for Reliable & High-Performance Comput., Illinois Univ., Urbana-Champaign, IL, USA

  • Venue:
  • IPPS '91 Proceedings of the Fifth International Parallel Processing Symposium
  • Year:
  • 1991
  • Targeted data prefetching

    ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

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Abstract

Reports the cache performance of a set of vectorized numerical programs from the Perfect Club benchmarks. Using a low cost trace driven simulation technique it is shown how a nonprefetching vector cache can result in unpredictable performance and how this unpredictability makes it difficult to find a good block size. Two simple prefetch schemes that reduce the influence of long stride vector accesses on cache performance and have better performance than the nonprefetching cache are presented.