Targeted random test generation for power-aware multicore designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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Full-chip simulation of multicore designs is an important element in the design verification cycle of a Chip Multiprocessor (CMP). Random tests are typically applied to the Multiprocessor (MP) in order to stimulate unexercised states of the machine. Completely random MP tests generally provide inadequate coverage, especially as the core count increases. In this paper the MP test program coverage is estimated by simulating the tests on a simple software model of the cache coherence protocol. Furthermore, equations are extrapolated to predict coverage as a function of core count based on constraints on addresses and test size. Finally a unique technique is introduced to expand the random component of MP tests while providing 100% cache line state transition coverage.