Accurately modeling superscalar processor performance with reduced trace
Journal of Parallel and Distributed Computing
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
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Trace-driven simulation is a widely practiced simulation method. However, its use has been typically limited to modeling of in-order processors because of accuracy issues. In this work, we propose and explore In-N-Out, a fast approximate simulation method to reproduce the behavior of an out-of-order superscalar processor with a reduced in-order trace. During trace generation, we use a functional cache simulator to capture interesting processor events such as uncore accesses in the program order. We also collect key information about the executed program. The prepared in-order trace then drives a novel simulation algorithm that models an out-of-order processor. Our experimental results demonstrate that In-N-Out produces reasonably accurate absolute performance (7% difference on average) and fast simulation speeds (115x on average), compared with detailed execution-driven simulation. Moreover, In-N-Out was shown to preserve a processor's dynamic uncore access patterns and predict the relative performance change when the processor's core- or uncore-level parameters are changed.