Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Hyper-Programmable Architectures for Adaptable Networked Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
In VINI veritas: realistic and controlled network experimentation
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
How to lease the internet in your spare time
ACM SIGCOMM Computer Communication Review
Cashmere: resilient anonymous routing
NSDI'05 Proceedings of the 2nd conference on Symposium on Networked Systems Design & Implementation - Volume 2
Tor: the second-generation onion router
SSYM'04 Proceedings of the 13th conference on USENIX Security Symposium - Volume 13
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Supercharging planetlab: a high performance, multi-application, overlay network platform
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
Revisiting Route Caching: The World Should Be Flat
PAM '09 Proceedings of the 10th International Conference on Passive and Active Network Measurement
Trellis: a platform for building flexible, fast virtual networks on commodity hardware
CoNEXT '08 Proceedings of the 2008 ACM CoNEXT Conference
CAFE: a configurable packet forwarding engine for data center networks
Proceedings of the 2nd ACM SIGCOMM workshop on Programmable routers for extensible services of tomorrow
Building a fast, virtualized data plane with programmable hardware
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
A Packet Generator on the NetFPGA Platform
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Scalable network virtualization using FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A survey of network virtualization
Computer Networks: The International Journal of Computer and Telecommunications Networking
ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
Proceedings of the ACM SIGCOMM 2010 conference
Chimpp: a click-based programming and simulation environment for reconfigurable networking hardware
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Customizing virtual networks with partial FPGA reconfiguration
ACM SIGCOMM Computer Communication Review
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Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has highlighted field programmable gate arrays (FPGAs) as attractive platforms for high performance network virtualization, these devices remain inaccessible to the larger networking research community due to the absence of user-friendly programming models. A programming model that can abstract the intricacies of the hardware platform while being aware of the underlying resource constraints is highly desirable. In this paper, we present ReClick, a framework to efficiently design and deploy reconfigurable data planes for FPGA-based network virtualization systems. A hardware-agnostic programming model is described that allows developers to focus on the virtual data plane semantics rather than the implementation details. The framework exposes interfaces similar to the popular software router development framework, Click, and promotes design reuse. Optimization strategies are included in ReClick which use similarities between virtual data plane configurations to implement multiple planes in an area-efficient manner. Data planes exhibiting up to 1 Gbps data rate have been automatically compiled and tested in hardware in a Net FPGA platform.