Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
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Transistor aging due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. State-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high performance demands, are at the front line to face this problem. In this paper, we present the design and mapping of a low-cost logic level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to late transition detector. The functionality of the sensor has been verified on a Virtex5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest. (~=1.3% area, ~= 1.6% performance, and ~= 1.5% power overhead).