A novel multithread routing method for FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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It has been observed in the past that the PathFinder routing algorithm runtime could be hampered by high fan out nets, primarily due to the time spent on the initialization of the priority queue. However, a solution has only been reported for routability/wirelength driven routers. In this paper, we report two heuristics that address the same issue for timing-driven routers. We show that on standard MCNC benchmarks, the proposed techniques can achieve 1.53 and 1.56 time speed up against the versatile placement and router (VPR), while achieving the same quality of result.